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Issue

SPI bus 3&4 on IGEPv2 (nowifi) issues

posted in Linux Kernel
Thursday, October 16 2014, 11:55 AM
0
eballatbo in the freenode.net#igep has been helping me with this issue and requested I post the details here.


End goal: to use SPI busses 1, 3 and 4 on the IGEPv2 (nowifi)

Reproduction:
* Download the IGEP Poky SDK & unpack/install
* Download the linux-omap-2.6 git kernel (branch: linux-2-6-37.y)
* Apply the patch to arch/arm/mach-omap2/board-igep0020.c to configure the mux (http://pastebin.com/bkYiSGQ4)
* Compile the kernel & install zImage and the modules to the stock IGEPv2 image on an SD card
* Cross compile a simple SPI program and run it (http://pastebin.com/GWTxVpSg - this program does a little config then reads 6 registers from an SPI slave)


Expected outcome:
Scope on the SPI lines shows:
* CS0 line going low,
* a clock signal on the CLK line,
* the read requests made on MOSI (3 bytes) and,
* a write result on MISO (1 byte).
The mac address stored in the registers of the SPI device are printed (one line per byte)


Actual outcome: Nothing happens. No errors and no activity on the SPI lines


This is repeatable with new compiler VM/new SD card/board combinations.


Running the following program also results in nothing (basically loop the read/write request 500 times so 3000 spi messages in total): http://pastebin.com/Q3vN85sy
However, running this program (http://pastebin.com/7hN5auVH) eventually (after ~200 iterations) results in the expected CS line going low and data on the CLK and MOSI lines showing activity (clock appears to be ~7kHz) and the data on the MOSI line appears random. Additionally, each iteration of the outer loop (j) seems to increase the length of the data and the number of 8 bit clock cycles.
Responses (5)
  • Accepted Answer

    Friday, October 17 2014, 11:37 AM - #permalink
    0
    We are using SPI4 from J990 connector on our IGEP RADAR product

    Could you test it with SPI4 bus ?

    It could be configured SPI4 MUX from userspace (debugfs) for quick test:
    cfg_igep0020() {
    
    	# mcbsp1_clkr.mcspi4_clk:
    	echo 0x101 > /sys/kernel/debug/omap_mux/mcbsp1_clkr
    
    	# mcbsp1_dx.mcspi4_simo
    	echo 0x001  > /sys/kernel/debug/omap_mux/mcbsp1_dx
    
    	# mcbsp1_dr.mcspi4_somi
    	echo 0x101  > /sys/kernel/debug/omap_mux/mcbsp1_dr
    
    	# mcbsp1_fsx.mcspi4_cs0
    	echo 0x001  > /sys/kernel/debug/omap_mux/mcbsp1_fsx
    }


    You could see pinout details about SPI4 on J990 connector at IGEPv2 HARDWARE MANUAL (page 58 / table 18)
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  • Accepted Answer

    Friday, October 17 2014, 01:19 PM - #permalink
    0
    I've had to configure it by re-building the kernel but:


    root@igep00x0:~# cat /sys/kernel/debug/omap_mux/mcbsp1*
    name: mcbsp1_clkr.mcspi4_clk (0x4800218c/0x15c = 0x0001), b y21, t NA
    mode: OMAP_PIN_OUTPUT | OMAP_MUX_MODE1
    signals: mcbsp1_clkr | mcspi4_clk | NA | NA | gpio_156 | NA | NA | safe_mode
    name: mcbsp1_clkx.gpio_162 (0x48002198/0x168 = 0x0004), b w21, t NA
    mode: OMAP_PIN_OUTPUT | OMAP_MUX_MODE4
    signals: mcbsp1_clkx | NA | mcbsp3_clkx | NA | gpio_162 | NA | NA | safe_mode
    name: mcbsp1_dr.mcspi4_somi (0x48002192/0x162 = 0x0101), b u21, t NA
    mode: OMAP_PIN_INPUT | OMAP_MUX_MODE1
    signals: mcbsp1_dr | mcspi4_somi | mcbsp3_dr | NA | gpio_159 | NA | NA | safe_mode
    name: mcbsp1_dx.mcspi4_simo (0x48002190/0x160 = 0x0001), b v21, t NA
    mode: OMAP_PIN_OUTPUT | OMAP_MUX_MODE1
    signals: mcbsp1_dx | mcspi4_simo | mcbsp3_dx | NA | gpio_158 | NA | NA | safe_mode
    name: mcbsp1_fsr.gpio_157 (0x4800218e/0x15e = 0x001c), b aa21, t NA
    mode: OMAP_PIN_OUTPUT | OMAP_MUX_MODE4
    signals: mcbsp1_fsr | NA | cam_global_reset | NA | gpio_157 | NA | NA | safe_mode
    name: mcbsp1_fsx.mcspi4_cs0 (0x48002196/0x166 = 0x0001), b k26, t NA
    mode: OMAP_PIN_OUTPUT | OMAP_MUX_MODE1
    signals: mcbsp1_fsx | mcspi4_cs0 | mcbsp3_fsx | NA | gpio_161 | NA | NA | safe_mode


    And it does even less than SPI3. In fact the CS0 line is low when it should be high?
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  • Accepted Answer

    Friday, October 17 2014, 05:30 PM - #permalink
    0
    If anyone has SPI3/4 working on an IGEPv2 could you image the SD card and send it to me please? (or just the kernel & modules/firmware)
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  • Accepted Answer

    Monday, October 20 2014, 10:58 AM - #permalink
    0
    Hi,

    Your SPI_CLK pin configuration is wrong
    It should be an input pin

    name: mcbsp1_clkr.mcspi4_clk (0x4800218c/0x15c = 0x0101), b y21, t NA
    mode: OMAP_PIN_INPUT | OMAP_MUX_MODE1
    signals: mcbsp1_clkr | mcspi4_clk | NA | NA | gpio_156 | NA | NA | safe_mode

    Cheers,
    Agusti
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  • Accepted Answer

    Monday, October 20 2014, 11:30 AM - #permalink
    0
    Tried it with the clk as an input. Same behavior.
    The reply is currently minimized Show
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